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Freescale Semiconductor /MK61F15WS /DDR /CR26

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Interpret as CR26

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0AGECNT0CMDAGE0 (0)ADDCOL 0RESERVED0 (0)BNKSPT 0RESERVED

BNKSPT=0, ADDCOL=0

Description

DDR Control Register 26

Fields

AGECNT

Age Count
CMDAGE

Command Age count
ADDCOL

Address Collision enable

0 (0): Disable

1 (1): Enable
RESERVED

Reserved
BNKSPT

Bank Split enable

0 (0): Disabled

1 (1): Enabled
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data